This invention relates generally to floating gate memory devices such as an array of flash electrically erasable and programmable read-only memory devices (EEPROMs). More particularly, the present invention is directed to a new and improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMs.
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such flash EEPROMs provide electrical erasing and a small cell size. FIG. 1 illustrates a prior art cross-sectional view of a flash EEPROM cell 10. The EEPROM cell is formed of a substrate 12, typically of a p-type conductivity, having embedded therein an n.sup.+ drain region 14 and an n-type double-diffused source region 16. The double-diffused source region 16 is formed of a deeply diffused but lightly doped n-junction 18 and a more heavily doped but shallower n.sup.+ junction 20 embedded within the deep n-junction 18. The deeply diffused n-junction 18 is typically formed by using a phosphorus implant, and the shallower n.sup.+ junction 20 is typically formed by using an arsenic implant after the phosphorus implant.
A relatively thin gate dielectric layer 22 (i.e., oxide having a uniform thickness of about 100 .ANG.) is interposed between the top surface of the substrate 12 and a conductive polysilicon floating gate 24. A polysilicon control gate 26 is insulatively supported above the floating gate 24 by an interpoly dielectric 28. A channel region 30 in the substrate 12 separates the drain region 14 and the source region 16. Further, there are provided terminal pins 15, 25, and 13 for applying a source voltage V.sub.S to the source region 16, a gate voltage V.sub.G to the control gate 26, and a drain voltage V.sub.D to the drain region 14, respectively.
According to conventional operation, the flash EEPROM cell of FIG. 1 is "programmed" by applying a relatively high voltage V.sub.G (approximately +9 volts) to the control gate via the terminal pin 25 and a moderately high voltage V.sub.D (approximately +5 volts) to the drain region 14 via the terminal pin 13 in order to produce "hot" (high energy) electrons in the channel 30 near the drain region 14. The source region 16 is connected to a ground potential (V.sub.S =0) via the terminal pin 15. The hot electrons are generated and accelerated across the gate dielectric 22 and onto the floating gate 24 and become trapped in the floating gate since the floating gate is surrounded by insulators. As a result, the floating gate threshold may be increased by three to five volts. This change in the threshold voltage, or channel conductance, of the cell created by the trapped hot electrons is what causes the cell to be programmed.
In order to erase the flash EEPROM cell of FIG. 1, a positive voltage V.sub.S is applied to the source region 16 via the terminal pin 15 while the control gate 26 via the terminal pin 25 is either grounded (V.sub.G =0) or biased to a negative voltage dependent upon whether the positive voltage V.sub.S applied to the source region 16 has a value of +12 V or +5 V. In a "12 Volt flash EEPROM" device, the bias condition of V.sub.S =+12 V and V.sub.G =0 is used. In a "5 Volt Only flash EEPROM" device, the bias condition of V.sub.S =+5 V and V.sub.G =-8.5 V is used. The drain region 14 is usually allowed to float. Under either of these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source region. The electrons trapped in the floating gate flow toward a cluster at the portion of the floating gate overlying the n.sup. + -type source region 16 and are extracted from the floating gate 24 to the source region 16 by way of Fowler-Nordheim (F-N) tunneling.
However, some of the electrons will remain trapped in the tunnel oxide adjacent the top surface of the substrate 12 as depicted in FIG. 1. This electron trapping will occur in the whole memory array and will tend to increase the erase time as a function of the number of program/erase cycles. As the number of program/erase cycles goes beyond the 100,000 number, the erase time required to erase every cell in the entire memory array to a certain threshold V.sub.T in order to pass the erase verify mode of operation will exceed the time limit of 10 seconds. It is generally assumed that if the entire memory array cannot be erased within the time limit of 10 seconds (i.e., 1 pulse/10 ms or 1,000 pulses), a cycling failure is considered to have occurred.
Therefore, the problem of electron trapping for such conventional EEPROM devices is of a major concern since it causes the erase time to be prolonged beyond the limit of 10 seconds, thereby significantly limiting the endurance of the cells. As used herein, the term "endurance" refers to the number of times the memory cells in the array may be re-programmed and erased. Consequently, the electron trapping problem greatly reduces the endurance of the cells to be less than 100,000.
The inventor has observed that the problem of electron trapping due to cycling did not occur in the 12 volt flash EEPROMs and was only a concern on the 5 Volt Only flash EEPROMs. By experimentation it was also found that in the 5 Volt Only EEPROM device the problem of electron trapping could not be prevented by simply reducing the tunneling field during the entire erase duration since the amount of erase time also has an effect on the electron trapping.
However, since the 12 Volt flash EEPROM device did not have the problem of electron trapping due to cycling, it was attempted to simulate the conditions on the 12 Volt flash EEPROM device on a 5 Volt flash EEPROM device by lowering the magnitude of the negative voltage on the control gate and increasing the voltage on the source through a load resistor. Thereafter, the 5 Volt flash device was cycled utilizing the condition of -5.5 volts applied to the control gate and +7 volts applied to the source via a 396 .OMEGA. load resistor through 30,000 cycles. The biases were so set because the erase time under same verify condition is about the same as the erase time under the typical present "5 Volt Only" erase condition (i.e., +5 V/-8.5 V/390 .OMEGA.) condition.
It was observed that under this condition (+7 V/-5.5 V/390 .OMEGA.) applied to the 5 Volt flash device, the erase time was slightly reduced (i.e., trapped electrons were being removed) for the first hundred cycles and remained substantially constant through 30,000 cycles. In other words, the problem of electron trapping had been eliminated.
By performing various measurements, it was determined that the tunneling electric field for the typical bias condition of -8.5 volts applied to the control gate and +5 volts applied to the source via the 396 .OMEGA. load resistor was higher at the beginning of the erase condition and lower towards the end of the erase condition as compared to the tunneling electric field under the condition of applying -5.5 volts on the control gate and +7.0 volts to the source through the same load resistor. As a result, the inventor has discovered that the problem of electron trapping can be reduced significantly or substantially eliminated by averaging the tunneling field throughout the erase duration.